Most memory devices can be categorized into two broad categories: volatile memory devices and non-volatile memory devices. Volatile memory devices include static random access memory (SRAM) cells and dynamic random access memory (DRAM) cells that require a power source to retain data. SRAM cells include a bistable flip flop circuit that needs an applied DC current to retain its bistable state, which determines the stored data value. A DRAM cell stores a data value as a charge on a capacitor that must be periodically refreshed. In either type of volatile memory cell, the stored data value is lost when power to the cell is turned off.
In contrast to volatile memory cells, the charge stored in non-volatile memory (NVM) cells is retained even if power is turned off. NVM cells typically include both a control gate and a floating (i.e., electrically isolated) gate, which can be programmed to store either a negative charge or a neutral charge. The amount of charge stored on the floating gate affects the threshold voltage of the flash cell (i.e., the voltage applied to the control gate at which the flash memory transistor turns on to allow current to flow through the NVM cell). When storing a negative charge (i.e., programmed), the negative charge stored on the floating gate prevents the NVM cell from turning on at the low control gate voltages used for reading the flash cell during a read operation. When storing a neutral charge (i.e., erased), the neutral charge stored on the floating gate allows the NVM cell to be turned on or off by the voltage applied to the control gate.
Memory devices are typically tested several times before they are sold to a customer to assure that they work properly. One such test, known as a wafer sort test, is performed after the memory devices are fabricated on a wafer and before the wafer is diced into individual die or “chips”. Wafer sort testing is used to identify non-functional memory devices that can be discarded (sorted out) during the subsequent dicing process. Additional testing may be performed during the fabrication process and/or after the memory devices are packaged.
FIG. 1 is a simplified diagram showing a wafer 100 during a typical wafer sort test procedure. Wafer 100 includes multiple memory devices 110 including arrays of memory cells (not shown) that are electrically connected using well-established metallization techniques to contact pads 115 located on an upper surface thereof. The wafer sort test process includes moving wafer 100 or a test arm 120 such that thin metal test probes 125 extending from test arm 120 are brought into contact with contact pads 115 of one or more selected memory devices 110. After contact is established power and test signals are transmitted from a tester (e.g., a work station) 130 to the selected memory device 110 via test probes 125, and test results are transmitted back from the selected memory device 110 to tester 130. The actual test results received from selected memory device 110 are compared by tester 130 with stored expected test results, and the selected memory device 110 is designated as either functional or defective based upon this comparison. This test is then repeated for all memory devices 110 on wafer 100.
FIG. 2 is a flow diagram illustrating the transmission of data between tester 130 and memory device 110 during a conventional external wafer sort test procedure. When probes 125 are brought into contact with contact pads 115 of a selected memory device 110 (see FIG. 1), power is transmitted via associated probes (Step 210) that causes the selected memory device 110 to “wake up” and perform an internal reset procedure (Step 215). After the selected memory device 110 is reset, the tester sends a first instruction (e.g., write) to the memory device (Step 220), and the memory device registers the instruction in an appropriate control register (Step 225). Subsequently, a series of addresses and/or data values are transmitted from the tester (Step 230) that are utilized to access memory locations (e.g., bytes) of the memory device for purposes of performing the designated instruction (e.g., read, write, erase, etc.; Step 235). When data is read from a particular memory location and/or other test functions are performed for which test data is generated, the memory device transmits the test results (Step 240), which are received and stored by the tester (Step 245). The process of transmitting address/data signals and performing the selected instruction is repeated for all memory locations until the entire memory device has been tested (Step 250), and then the address/data transmission process is restarted and repeated for each subsequent test instruction until all instructions have been completed (Step 260). Upon completion of the test instructions (or, alternatively, upon receipt of an error message during one of the instructions), the tester designates the selected memory device as either “good” or “bad” for the wafer sorting process.
A problem associated with the conventional external test procedure described above is that the transmission of instructions, address/data signals and test results between the tester and the selected memory device is slow, thereby requiring a relatively long period of time to perform the wafer sort test. This long test period slows down production, and ultimately increases the cost of the memory devices.
What is needed is a memory device that facilitates the performance of sort testing in a minimum amount of time, thereby reducing production costs.